The present invention relates to computer system cache memory access, and more specifically, to a system including a prefetcher configured to detect data streams that stride multiple cache lines and configured to switch between multiple threads in a multithreading system or environment.
In the field of computers or computing systems, it is common to prefetch instructions or data from a memory location to a local cache memory in order to improve performance. In simultaneous multithreading configurations, where data streams are executed in parallel, prefetching strategies are more complex than single thread prefetching. Prefetching in multithreading environments can thus involve incorporating additional complexity, such as by adding more memory to a chip or adding hardware to the chip.